The present invention generally relates to a process for producing integrated circuit devices, and more particularly to a method for forming an epitaxial cobalt silicide layer on MOS devices.
Cobalt silicide (CoSi2) has been widely accepted as an electrical contact and interconnect material for use in forming MOS devices. Significant reduction in parasitic electrical resistance is achieved with the formation of a CoSi2 layer, which therefore enhances drive-current and speed of the devices. One commonly known method of forming a CoSi2 layer is a self-aligned silicide (salicide) process, in which cobalt is deposited on a MOS structure, and reacts with the exposed silicon and polysilicon of the MOS structure in a heated environment to form a silicide layer. The unreacted metal is then removed from the MOS structure by using a selective etching process, leaving the silicide over the gate and the source/drain region.
As devices are scaled to sub-0.18 xcexcm and beyond, the requirements for salicide process become more stringent. In order for devices to operate in the deep sub-micron regime, shallow source/drain junctions are incorporated to prevent junction xe2x80x9cpunch-throughxe2x80x9d and reduce the effect of drain-induced barrier lowering (DIBL). The presence of non-uniformity or interface roughness at the silicide-silicon interface is detrimental to the integrity of shallow junctions, and it could result in excessive junction leakage current. As a result, forming epitaxial CoSi2 has become of critical importance, especially for deep sub-micron devices.
One known method of forming epitaxial CoSi2 involves the use of a thin metal interlayer between the cobalt layer and silicon substrate. Another method includes depositing a thin titanium nitride or titanium tungsten film as a capping-layer on top of the cobalt layer. Both of these methods require subjecting their respective structures to heat treatment processes to form cobalt silicide. These known methods require additional processing steps and/or an additional sputtering chamber and target for depositing the interlayer or the capping-layer. Moreover, extra cleaning steps are also required to remove the additional interlayer and capping-layer upon silicide formation. Consequently, these methods further result in increased process cycle time due to the additional processing steps involved.
The present invention is directed to a method for forming an epitaxial cobalt silicide layer on a MOS device. The method includes the step of sputter depositing cobalt in an ambient, forming a first layer of cobalt silicide on gate and the source/drain regions of the MOS device. Subsequently, cobalt may be sputter deposited again in an ambient of argon to increase the thickness of the cobalt silicide layer to a second thickness.